PCI is an open, non-proprietary local bus standard offering high performance for multiple peripheral devices. The standard is becoming widely accepted throughout the computer industry. A complete PCI Revision 2.1 specification is available from PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214, the information of which is incorporated herein by reference. PCI works as a processor-independent bridge between a CPU and high-speed peripherals and allows PCI cards built today to be used in many different systems. The PCI standard specifies a configuration address space which is designed to accommodate many different types of computer systems, including desk-top, portable, and server computers. The PCI standard allows servers to offer more I/O connections, expansion slots, and the isolation of high bandwidth traffic from lower bandwidth traffic. The ability to identify each PCI device and dynamically assign system resources to the PCI devices enables configuration software to construct optimized system memory and I/O address space maps that remain free of resource conflicts.
To meet the requirements of these various architectures, the architects of the PCI configuration address space implemented a template as part of the PCI standard. This template consists of a block of 256-byte-wide contiguous addresses into which all of the PCI configuration space registers are mapped. 64 bytes are used for a header called a Configuration Space Header, which comprises configuration space registers. 192 bytes are used for device dependent regions.
FIG. 1 is a pictorial view of the 64 byte register layout of a Type 00h PCI Configuration Space Header (PCI Rev. 2.1). All PCI Rev 2.1 compliant devices that implement a Type 00h header must support this layout. Of this 64-byte configuration space header region, the first 16 bytes are assigned to the PCI Device Independent Region, and the remaining 48 bytes are assigned to the PCI Device Header Type Region. This register set controls how a PCI device's memory and I/O functions are mapped into a system's memory and I/O address spaces when the system is reset.
Several configuration space registers within the PCI Device Header Type Region, called "Base Address Registers", are used to communicate information which specifies either memory or I/O address space requirements for the corresponding functions during configuration. (Also known as BARs, Base Address Registers store the size of a function's address space and allow the system to allocate the starting address at which that function's required address space begins.) This information is used by configuration software to initialize the device with non-conflicting resources.
As can be seen in FIG. 1, the PCI Device Header Type Region includes Base Address Registers (BARs) in locations 10h through 24h. The first BAR location is 10h. Depending upon the word length of this first BAR, the second BAR may be located at either 14h or 18h. The offset location of any BAR other than the first depends on the size of the previous BARs.
In each of the up to six base address registers, bit 0 is an address space type indicator which is a ZERO for allocating memory, and a ONE for allocating I/O space.
The definition for base address bits for allocating memory is shown in FIG. 2. When bit 0 is ZERO (indicating that memory is to be allocated), bits 1 and 2 specify the memory type and bit 3 denotes whether or not the device's memory space is prefetchable. Bits 4 to 31 indicate the size of a memory space region assigned to the device. This is implemented by setting to the value of ONE that bit representing the size in powers of 2 of the block of memory space requested by that device. For example, if a device is set to request a 64 kilobyte block of memory (216 bytes), then bit 15 (the 16th bit) will be the first bit above bit 3 set to ONE, with all bits between bit 3 and bit 15 being set to ZERO.
Because these Base Address Registers are reset upon power-up, any bit set to ONE must be hard-wired (stored by non-volatile means).